Senior ASIC Design Efficiency Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

We are now looking for a Senior ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!

What you'll be doing:

• Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
• Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
• Develop innovative memory subsystem designs to extend the state of the art performance and power efficiency.
• Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.

What we need to see:

• BS Degree in CompE, EE, CS, or equivalent experience
• 5+ years of relevant industry experience
• Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog
• Strong interpersonal skills are required along with the ability to work in a diverse product oriented team.

Ways to stand out from the crowd:

• Strong analytical thought process and outstanding debug skills along with strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
• Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks
• Infrastructure development, use of AI to support design and verification development
• Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs.
• Experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.

#LI-Hybrid

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.Applications for this job will be accepted at least until November 17, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.